Alex Chen

Full-Stack Analog IC Engineer
University of Macau & Southern University of Science and Technology

About

I am a Ph.D. candidate in Electrical and Computer Engineering at the University of Macau (joint doctoral program with Southern University of Science and Technology). My research focuses on AI-assisted analog circuit design automation, combining reinforcement learning with traditional circuit design methodologies to accelerate the analog IC design process.

Infrastructure Setup & Maintenance → Analog Circuit Design & Testing → AI-Assisted Design Automation

Education

University of Macau (Joint Doctoral Program with SUSTech) Sep 2022 – Present
Doctor of Philosophy in Electrical and Computer Engineering
Macau, China
Carnegie Mellon University Jan 2020 – May 2021
Master of Science in Electrical and Computer Engineering
Pittsburgh, PA, United States
Imperial College London Sep 2018 – Sep 2019
Master of Science in Analogue and Digital Integrated Circuit Design
London, United Kingdom
Shanghai University Sep 2014 – Jun 2018
Bachelor of Engineering in Microelectronic Science and Engineering
Shanghai, China

Research Projects

AI-Assisted Analog Circuit Design Automation
Advisor: Prof. J. Smith, Southern University of Science and Technology Jun 2023 – Present
  • Developed design intent driven multi-agent reinforcement learning with current-transient automatic clustering, achieving significant convergence speedup over manual clustering, integrated AHP-based reward weighting to align optimization with designer preferences.
  • Introduced a framework integrating evolutionary strategies with data-driven clustering, achieving substantial convergence speedup and reduction in confidence interval width for stable optimization.
  • Proposed a functionality-driven grouping strategy for multi-agent RL, reducing simulation requirements and achieving faster convergence through improved credit assignment.
  • Developed critic-free reinforcement learning algorithm with direct parameter space mapping, enabling rapid exploration in large combinatorial spaces and significant convergence speedup over state-of-the-art RL methods.
High-Efficiency Capacitive Power Converter for Universal AC Input
Advisor: Prof. J. Smith, Southern University of Science and Technology Jan 2022 – Jun 2022
  • Designed complete control loop including idle power reduction control and multi-phase switched-capacitor converter control, achieving low quiescent power and high peak efficiency for universal AC input.
  • Implemented adaptive power management algorithm dynamically adjusting operating phases based on load conditions, reducing standby power consumption while maintaining fast transient response.
Ultra-high Frame Rate Ion Imager with Column-wise ADC for Biosensing
Advisor: Prof. R. Williams, Imperial College London Dec 2018 – Sep 2019
  • Designed peripheral circuits for large-scale ISFET array in advanced CMOS process, featuring high-resolution current-mode ADC and current conveyor-based pixel readout.
  • Implemented digital backend flow from HDL to physical layout using industry-standard EDA tools, achieving successful DRC and LVS verification.

Publications

  1. A. Chen, L. Wang, Y. Zhang, M. Liu, K. Park, D. Brown, T. Lee and J. Smith, "Constraint-Aware Multi-Objective Neural Architecture Search for Automated Analog Circuit Sizing," ACM/IEEE Design Automation Conference (DAC), under review, 2026.
  2. A. Chen, L. Wang, Y. Zhang, M. Liu, D. Brown, T. Lee and J. Smith, "Topology-Guided Multi-Agent Optimization with Transient Feature Clustering for Power Regulator Design," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, under review, 2026.
  3. R. Kim, A. Chen, D. Brown, W. Zhao, C. Huang, T. Lee and J. Smith, "A 1W Universal Input Capacitive AC-DC Converter with Multi-Phase Switched-Capacitor Stage," IEEE J. Solid-State Circuits, pp. 1-12, 2025.
  4. A. Chen, L. Wang, Y. Zhang, M. Liu, Q. Xu, T. Lee and J. Smith, "Clustering-Enhanced Multi-Agent Reinforcement Learning for Analog Circuit Parameter Optimization," Design, Automation and Test in Europe Conference (DATE), Verona, Italy, 2026, Accepted.
  5. L. Wang, A. Chen, Y. Zhang, M. Liu, S. Patel and J. Smith, "Functionality-Driven Multi-Agent Policy Optimization for Power Regulator Sizing," Association for the Advancement of Artificial Intelligence (AAAI), Singapore, 2026, Accepted.
  6. A. Chen, L. Wang, M. Liu, Y. Zhang, D. Brown, T. Lee and J. Smith, "Critic-Free Reinforcement Learning with Direct Parameter Mapping for Large-Scale Analog Circuit Sizing," IEEE International Symposium on Circuits and Systems (ISCAS), Shanghai, China, 2026, Accepted.
  7. R. Kim, A. Chen, D. Brown, C. Huang, T. Lee and J. Smith, "An 85-264Vac Input Capacitive Power Converter with Idle Power Reduction and Multi-Phase SC Stage," IEEE International Solid-State Circuits Conference (ISSCC), San Francisco, CA, USA, 2024, pp. 1-3.
  8. P. Yang, D. Brown, A. Chen, T. Lee, S. Patel and J. Smith, "A Battery-to-High-Voltage Hybrid Boost Converter for Piezoelectric Actuators," IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 70, no. 10, pp. 3857-3861, Oct. 2023.

Patents

  1. J. Smith, A. Chen, W. Zhao and T. Lee, "A Voltage Reference Circuit, Power Supply and Electronic Device," CN000000001A, Aug. 2022.
  2. R. Kim, A. Chen, J. Smith, T. Lee, S. Patel and D. Brown, "Conversion Circuit and Power Conversion System," CN000000002A, Jun. 2023.
  3. A. Chen, J. Smith, L. Wang, M. Liu, Y. Zhang and K. Park, "Multi-Agent Reinforcement Learning Optimization Method for Analog Circuits," CN000000003, Filed Sep. 2025, Pending.

Technical Skills

AI/ML Tools PyTorch, Ray RLlib, Reinforcement Learning Algorithm Development
Analog Design Cadence Virtuoso, Cadence Spectre AMS, Synopsys TCAD, Synopsys DC, Mentor Calibre
Digital Design Cadence Innovus, Cadence Genus
Infrastructure Linux Server Administration, LDAP Configuration, TrueNAS Storage, Network Configuration, PDK Version Control